(1) Field of the Invention
The present invention relates to an inspecting method, an inspecting apparatus, and a method of manufacturing a semiconductor device, and more particularly to a method of and an apparatus for inspecting a wafer for a pattern defect, a foreign matter deposition, or the like, and a method of manufacturing a semiconductor device, which includes such an inspecting process.
(2) Description of the Related Art
In the process of manufacturing semiconductor devices, inspecting apparatus including an appearance inspecting apparatus, a surface foreign matter inspecting apparatus, etc. are used to inspect wafers for pattern defects, foreign matter depositions, or the like (hereinafter referred to as “defect”). For determining the cause of a defect, it has been customary to detect the positional coordinate of the defect on a wafer or confirm the shape of the defect, the size of the defect, etc. with a scanning electron microscope (SEM).
According to the conventional inspecting process, chip areas (hereinafter referred to as “effective chip area) on wafers where chips to be used as products are formed are selectively inspected. An effective chip area usually contains many patterns of devices and interconnections. Though a defect such as a pattern peel, a particle deposition, or the like is found in the effective chip area by the inspecting process, the information of the defect is not sufficient to specify the source of the defect or determine the cause of the defect.
A detailed inspection of a wafer with an SEM often reveals the source of a defect found in a peripheral wafer area outward of the effective chip area. In order to determine the source of a defect for optimizing the process conditions and performing maintenance of the semiconductor device fabrication apparatus for an increased chip yield, growing importance has recently been attached to the inspection of peripheral wafer areas (see, for example, Japanese Unexamined Patent Publication No. 2006-105946).
Of the chips on a wafer, i.e., of the chips in the effective chip area of the wafer, those chips which are positioned in a peripheral zone of the effective chip area are more likely to suffer defects. In view of this tendency, there has heretofore been proposed an inspection system for inspecting chips in greater detail in the peripheral zone of the effective chip area of a wafer than in a central zone thereof and for shortening the period of time required to inspect the wafer (see, for example, Japanese laid-open patent publication No. 11-219997).
If the peripheral wafer area outward of the effective chip area of a wafer, as well as the effective chip area thereof, is to be inspected for greater wafer inspection reliability, then the amount of data processed by the inspecting apparatus is so large and the period of time required to inspect the wafer is so long that the throughput of the semiconductor device fabrication process is low.
Inspecting apparatus or inspecting systems that are not designed to inspect the peripheral wafer area outward of the effective chip area of a wafer are incapable of automatically inspecting the peripheral wafer area in the same manner as they inspect the effective chip area. It will take a large expenditure of time and labor to inspect both the effective chip area and the peripheral wafer area with those inspecting apparatus or inspecting systems.